Waterproof Connectors Now Available

SV Microwave waterproof connectors

Spirit Electronics now offers SV Microwave’s wide range of IP 68 water-protected interconnect products designed to withstand rigorous environments and harsh elements. SV’s line of waterproof connectors include hermetically-sealed connectors to the 1 x 10-8, making them ideal for high pressure, vacuum applications and the prevention of liquid or gas leakeage. Ingress Protection ratings are used to specify the environmental protection of enclosures and casings around electronic products.  

Common applications of these products include:

  • RF test and measurement
  • Military and aerospace
  • Industrial process control
  • …and more. 

Wafer Lot Acceptance to Mil-Std-883, Method 2018

Do you need Wafer Lot Acceptance to Mil-Std-883, Method 2018? This post explores the purpose and importance of this standard when performing electronics failure analysis.

What is MIL-STD-883

MIL-STD-883 is US military test standard for testing microelectronic devices. The objective of MIL-STD-883 is to identify devices suitable for use within military and aerospace electronic systems that withstand the harmful effects of natural elements and conditions.

Wafer Lot Acceptance to Mil-Std-883, Method 2018

The Mil-Std- 883, Method 2018 specifies sampling procedures for die selected from the wafers or die already packaged. In this post, we dive into the purpose and processes required by this standard.

Scanning Electron Microscope (SEM) Inspections are defined in Mil-Std-883, Method 2018, and form part of a Wafer Lot Acceptance (WLA) plan. The purpose of this standard is to ensure metallization layers in the integrated circuit (IC) do not suffer from systemic processing problems.

Although WLA is not typically cited for industrial environments, the mission-critical components in the military and aerospace marketplaces for Method 2018 are commonplace as a requirement for integrated circuit wafers and die.

The Importance of Method 2018

One purpose of Method 2018 is to ensure a wafer processing lot has metal layers that are at least 50% of their designed cross-sectional area for current densities.

Metal layers processed on a planar technology are typically not a concern; however, in non-planarized processes, the oxide steps can result in thinning of the metal and therefore decrease the cross-sectional areas.

These metal step coverage concerns can result in failures if the cross-sectional areas are too thin for the designed current density criteria required by Mil-PRF-38535 and lead to localized current hot spots that could result in blown metal lines or long-term failures from electromigration.

Method 2018 is focused on characteristics of the metal layers that are evaluated across the wafer lot, and not random defects, such as scratches, smeared metal, etc.

Statistically, a very large sample size would be required to validate a particular wafer lot. The Mil-Std- 883, Method 2018 specifies sampling procedures for die selected from the wafers or die already packaged. A sampling of 8 dies is required if there is wafer lot traceability or 22 samples of a population of devices that do not have traceability back to the wafer lot.

The metal inspection can begin, once the samples have been selected. Typically samples are pulled from completed wafer lots, although Mil-Std- 883, Method 2018 does provide some guidelines for pulling samples before final glassivation.

Assuming the samples are from completed wafers, the top glassivation layer will need to be removed before the metal lines can be SEM inspected. The maximum SEM magnification required by Method 2018 is 50,000x, with an SEM resolution of 250 angstroms or less. For the SEM inspection, the use of a conductive coating on the specimen is discouraged. Thankfully, a good Field Emission SEM (FE-SEM) easily meets all these requirements.

The next layer of metallization will need to be uncovered and inspected after the top layer metallization has been inspected. The top metal and the glassivation layer beneath the top metallization must be removed to inspect the next layer of metallization. This selective deprocessing should not disturb the underlying metal layer to allow the inspection of the next metal layer.

This process is repeated for each metal layer, meticulously removing the top metal layer and oxide to get to the next metal layer without causing any damage. It is possible, using dry etch techniques, to expose multiple metal layers at a time; this is allowed under the regulations of Method 2018 and can increase the efficiency of the inspection process, saving time and money.

Another requirement of Mil-Std-883, Method 2018 is the performance of a cross-section of the sample, either by lapping or cleaving. This additional step is performed at areas of interest, based upon the top view examination already performed, to allow an accurate measurement of the metallization thickness on a planar region, the metallization thickness over the step coverage, and a view of any suspect structures or process artifacts (but still not random defects). Obviously, cross-sections in the x- and y-planes are the minimum needed, and on occasion, a customer may also provide areas of interest (based upon their knowledge of a specific structure that might be unique).

The SEM inspection itself is straightforward, but the deprocessing of each metal layer and oxide to the next metal requires a lab with considerable experience in this area of expertise. Most non-planar processes only have three levels of metal or less, however, the irregularities in the metal heights (mountains and valleys if you will) can be considerable.

To perform a proper inspection, it may be necessary to etch the glassivation layer in the valley to expose the metal therein, while leaving the metal atop the “mountain” intact. Although the latest version of Method 2018 does not require inspection of planarized processes, there are some IC users who still require this inspection. In these cases, there can be upwards of 8 layers of metal to be inspected and subsequently removed.

Furthermore, the mainstream wafer processes are now including some or all copper metallization in IC manufacturing. The process of removing copper metallization is much different than that of aluminum, and if there is a subsequent layer of aluminum under the copper layer, the deprocessing also needs to take that under consideration.

Any misprocessing when removing the metal and glass layer will be compounded by the ensuing deprocessing steps, potentially rendering the sample useless for the examination of the lower metallization levels. Method 2018 foresaw such issues and allows the sampling of a second die (adjacent to the first one sampled) as a replacement).

It is still necessary, though, to deprocess the top levels of metal to resume the inspection of the lower levels. This can be a very costly process if too many mistakes are made, or for some labs, not even feasible. Obviously, each time a sample has to be started over, there will be a delay in the time to finishing the inspection and hence a delay in releasing the wafer lot for production.

While no electronic failure analysis lab will deprocess every die perfectly, it is obviously desirable to select a lab with a successful track record, one that will minimize costs and time delays. As such, the selection of the lab to perform the SEM inspection should focus on reputable labs with the experience, knowledge, and capability to meet your needs.

Mil-Std-883, Method 2018 specifies the requirements for the SEM Inspection of metallization layers of integrated circuits. It is a very complete document detailing how to prepare for and inspect the metallization layers in order to accept a wafer lot. One of the key ingredients is working with a failure analysis laboratory that you know has the appropriate equipment, technical know-how, and experience in deprocessing and inspecting to this standard.

Printed Circuits Defects – Analysis and Detection

A failure analysis lab employs a wide variety of techniques to search for defects in integrated circuits. Last week, we had seen what goes on inside a failure analysis lab and today we’ll take a look at the different types of printed circuits defects and what class of methods are used to analyze them. It should be noted that any printed circuits defects analysis is preceded by a thorough examination of the facts accompanying the detection of the failure and only after the engineers know what they’re looking for, do they settle down to apply specific failure analysis techniques.

Types of Printed Circuit Board Defects

There are three types of broad defects which can occur in printed circuit boards. Physical disruptions in the material, flaws in the makeup of the material and electrical construction problems. Each of these requires a different approach in detection and shows different symptoms which can be uncovered by analyzing the circumstances surrounding the failure.

Physical disruptions in the material are the most obvious. Not that they’re easy to detect, but they’re easiest for a layman to understand. They occur when the integrity of the chip breaks down in some places. Fatigue cracks and corrosion are two examples of this type of breakdown. Frequently, the defects are tiny and can’t be seen without assistive technologies.

Dye penetrant testing is an excellent way to detect these failures. The chip is stained with a coloring material that reveals cracks and faults. The specific characteristics of these faults give engineers a clue as to what type of fault it is.

The second type of flaw is one which deals with the purity of the materials. Semiconductor materials are manufactured to very precise specifications with just the correct amount of trace minerals necessary for certain properties. Deviations from this will cause the chip to behave in unexpected ways. Since the deviations can be tiny, precise measurements using various emission techniques are used to determine the extent of the flaws.

The third type of flaw deals with the many electrical faults that can occur on the millions of connections on any given chip. It’s remarkably difficult to detect these flaws, but one of the starting points is to figure out which portion of the chip is overheating. Fluorescent imaging, as well as liquid crystal imaging, can be used to find out where the heat is being generated, though this doesn’t automatically mean that the flaw is present in that area as it could occur somewhere “up river.”

Printed circuits defects require a thorough understanding of how chips work. It’s an exact science as well as an art – and one in which new methods are constantly being innovated.

Using Electron Microscopy in Metallurgical Failure Analysis Lab Services

Understanding why things fail is critical to preventing failure in the future. Whether it is a single catastrophic failure whose root cause needs to be understood to prevent future critical failures or a test run of a prototype that is about to go to production understanding the root causes of failure are essential.

Mechanical failures, in particular, can be complex and difficult to understand. When there is a mechanical failure of a material, several tests and images must be taken in order to understand the cause of the failure. Taking your sample to a lab with electron microscopy services can help you dig down further to find out where your failure might have occurred.

Advantages of Electron Microscopy in Mechanical Tests

The failure analysis engineers in our scanning electron microscopy lab are experienced experts in the use of this analytical technique.   Electron Microscopy has several advantages which can be leveraged for performing the mechanical analysis. First and foremost is the resolution. Scanning Electron Microscopes (SEMs) are a valuable failure analysis tool in the hands of an experienced technician. Not only are they capable of producing much higher magnification than an optical microscope, but they also have an array of analytical tools that can be used to enhance investigations.

The enhanced resolution allows an investigator to be able to look down to the atomic scale and look at developing grain boundaries, crystalline formations and obtain element analysis. This means that looking at the right set of images could point directly to the root cause of a failure at the molecular level.

Fatigue Analysis

Failures can happen quite a few different ways. When looking at a failed component, detailed images can show materials experts clues to what might have been the cause. For example, a material that fails due to one powerful tensile force is going to look very different than something that experienced high cycles of very low forces, or damage due to low-frequency vibration. A skilled lab with an SEM can take detailed images that will determine the differences between these two events.

SEMs are capable of taking images using much lower voltages. This allows the microscope to take images showing much more detail along the surface of the failure. The process is referred to as surface topography.

When a part fails due to fatigue, be it high tensile force or low force repetitive failure, the surface of the material will stretch and have formations called striations. These formations will indicate the cause of the failure. Being able to see as much detail as possible when looking at fatigue striations will allow engineers and materials experts to determine what mode or modes might have caused the part to fail. All of this is made possible with images taken by skilled SEM lab operators.

Structural Analysis and Crack Propagation

Another type of failure that can occur to the material is cracking. Cracks generally form at the micro-level along formations in a material called a grain boundary.

When one material is combined with another (in metallurgy this is called alloying), the two dissimilar materials will bond together in groups. The easiest way to think of this would be to picture a rice cereal treat. The full bar is made up of small pieces of cereal, you can see the boundaries between the rice granules. A similar thing happens in metals.

If materials are combined properly then the individual “grains” will be small. There will be short boundaries between the two grains. In some cases, the grains are large and lead to long boundary lines between them.

When a material is subjected to stresses, cracks can form along these boundaries. Over time, a crack will follow this grain boundary, becoming larger and larger until the part fails.

Well taken images from an electron microscope will allow materials experts to view the granules and the grain boundaries of the material. This can clue them into where cracks in the material can form, how a crack propagated through the material and was the material at fault for the failure.

Consider Your Sample Size

One thing to consider when thinking about using a lab for electron microscopy is how your sample is. Sample size can determine if testing is able to be done in a way that will not damage the sample, allowing other testing techniques to be used on it in the future.

Samples that are too large will often need to be cut to the proper size for the electron microscope. If this is done, it could compromise the sample for future use. It is very important to know your lab’s capabilities and what sample sizes they can handle before testing begins.

Using an experienced and skilled lab for your SEM failure analysis could mean the difference between root cause determination of the failure or waiting around for further failures to conduct more testing. Contact us today for about Electron Microscopy services!

Choosing the Right Microelectronics Failure Analysis Lab

Computers used to take up entire rooms to perform what we would consider today rather rudimentary calculations. As computing power increased, the size of the computers decreased. What was once an easily spotted blown tube transistor became very difficult to see electron leakage through a PNP junction.

Enter the world of microelectronics. Every mobile electronic device today is powered by microelectronics. They need to be small, fast and reliable. They also need to be durable. When things go wrong with them, we want to know what caused the failure and how it can be fixed to make our electronics as reliable as possible.

What Are Microelectronics?

An understanding of where microelectronics might fail begins with an understanding of what microelectronics are. In short, microelectronics are circuits that are constructed at the micrometer-scale, perhaps even smaller.

The heart of every computer is the transistor. An easy way to think of it is the more computing power you wish your computer to have, the more transistors you need in its CPU. This means that in order to make a more powerful computer but keep the size of the computer the same, there is a need to figure out a way to make transistors smaller and smaller; enter semiconductor devices.

How We Make Transistors From Semiconductors

As computers advanced and the demand for computing power increased, it became necessary to figure out a way to create a transistor out of something that could be very small. Engineers were able to figure out a way to create the effect of a transistor by using a combination of metals and semiconductor materials.

Transistors created using this method are the foundation of the integrated circuitry controlling all of our electronic devices today. They are made using complex fabrication techniques that allow engineers to make transistors so small they cannot be seen by the naked eye.

When Things Go Wrong

Inevitably, as with any production method, things can go wrong. When this happens, chips and devices fail. This is where the need for accurate failure analysis comes in to play. In order for engineers to understand the causes of the circuit failure, special equipment and experts in using that equipment are needed to do a detailed analysis of the broken part.

There are quite a few places that microelectronics can fail:

  • Fabrication Process Failures – these are generally defects that exist when the circuit is created. Complex chemical and electrical processes are used to create microelectronics on a small scale. Small impurities in the materials, the wrong concentration of etching or cleaning chemicals, or plasma etching process issues- all of these can contribute to manufacturing problems which cause IC and device failure.
  • Operational Parameter Issues – Issues like this could be design flaws that allow voltages or currents too high for ICs to handle. Things like high operating temperatures or shock damage that exceeds what the IC can withstand are other examples of operational parameters. Evidence of all of these can be seen using the right analysis techniques.
  • Design Flaws – These are issues with the circuit itself not performing up to specification due to an improper layout.
  • Knowing how to look is a skill. Labs who are experienced with microelectronic failure analysis have a feel as to where in the circuit to begin their investigation. This can save time and money on the device manufacturer’s part as the flaw will be spotted sooner. This means using the right equipment to do the imaging, using the right processes to take a cross-section of devices if needed, and how to interpret the results.
  • Knowing where to look is as important as knowing how to look. Experienced technicians will be able to have a feel where inside the IC that these types of failures can occur and look in the right spots sooner than less experienced labs.

Imaging and Failure Analysis

Once the device fails, the investigation into what caused the failure begins. This is where the experts come into play. Choosing a lab that has both the necessary equipment and expertise in the area can be the difference between spotting a flaw and fixing it, or having to scrap a design and go back to the drawing board.

Failure Analysis on the micro scale is not something that is done easily. Remember, these devices are small- so small that even regular microscopes are not able to see them in some cases. This means two things:

As you can see, microelectronics can be complicated devices. When trying to determine the root causes of failure, failure analysis experience is key. Choose an electronics failure analysis lab that has the right equipment and experience in the field. Spirit Electronics is here to help you decipher what is needed to solve your problem.

Scanning Electron Microscope – Explore the Nanoscopic World

Modern semiconductors and integrated circuits are built with geometries measured in terms of angstroms and nanometers, and defects on these devices may be completely invisible under an optical microscope. For uncovering even the smallest defects, Spirit offers scanning electron microscopy services, providing a crisp, clear image of any anomaly imaginable. Learn more.

The electronic component failure analysis process can be long and arduous, involving a wide variety of tools and techniques to uncover the root cause of a malfunction.

Ultimately, however, the culminating moment of any investigation is the moment where an analyst can produce a clear, sharp photograph as incontrovertible evidence of the existence of a defect. Indeed, not only in failure analysis but in any of the sciences, it can be said that “seeing is believing” and a detailed picture can remove any shadow of a doubt as to the nature of an object.

In the case of failure analysis, a good image can help to identify the type of corrective action that must be implemented to resolve a recurring problem. Large defects, like those that result from severe electrical overstress, can often be seen clearly under an optical microscope; however, modern integrated circuits are built with geometries measured in terms of angstroms and nanometers, far below the resolution threshold of optical microscopy. Defects on these devices may be completely invisible under an optical microscope. For uncovering even the smallest defects, Spirit offers electron microscopy services, providing a crisp, clear image of any anomaly imaginable.

The way an electron microscope differs from a visible light microscope can be reasonably inferred from the names of the two techniques; where visible light microscopy focuses the rays of light that our eyes perceive normally using optical glass lenses, electron microscopy uses strong electromagnetic fields to produce, shape, and focus a beam of electrons onto the surface of a sample. As the electron beam interacts with the sample, several phenomena occur; for the microscopist, the most important of these phenomena is the generation of secondary and backscattered electrons.

By scanning the electron beam across the surface of a sample and collecting the secondary and backscattered electrons, the electron microscope can construct an image of the sample. Since an electron has a far shorter wavelength than a photon of visible light, the diffraction limit of the tool is much smaller; resolutions of several angstroms can be achieved, where visible light is limited to roughly two-tenths of a micron. This increased resolution makes it possible for an analyst with access to a good electron microscope in his or her lab to find nano-scale defects like gate oxide pinholes or crystalline dislocations.

Tuning the electron microscope detector to gather mostly secondary or mostly backscattered electrons can produce different data, showing greater implied topography or accentuating elemental differences, respectively. Electron microscopes also boast a much greater depth of field than optical microscopes, making it possible to keep large three-dimensional structures in focus across larger distances – a benefit when performing inspections of circuit assemblies or deprocessed integrated circuits.

Electron microscopy services are not limited to imaging; in addition to the generation of secondary and backscattered electrons, bombarding apart with a high energy electron beam also produces characteristic x-rays as a result of the excitation and relaxation of the electrons orbiting the atoms of the sample. The energies of these characteristic x-rays are uniquely tied to the element from which they are emitted; by using an energy dispersive spectrometer (EDS), these x-rays can be collected and the material composition of the sample can be identified. The EDS can be used to positively determine the makeup of contaminants, measure the constituents of an alloy to be compared to a specification or other reference, or generate an elemental “map” showing where certain elements are concentrated on a sample.

The electron microscope can also be used as an isolation tool for certain types of defects. The electrons that make up the focused beam of the tool are negatively charged, and therefore will experience some degree of attraction or repulsion depending on the charge present on a sample. By intentionally placing a charge on a sample (for example, connecting a voltage source to a failing signal on an integrated circuit), it is possible to change the way that the electron beam interacts with the device, creating differences in image contrast that can highlight a defect. This technique, known as “charge contrast” or “voltage contrast”, can be invaluable in finding certain types of anomalies, especially those that cause open circuits. Indeed, certain defects may not require any additional setup at all; the passive charge contrast resulting from the electron beam itself may be enough for an analyst to pinpoint a defect.

Electron microscopy allows our electronic failure analysts to take incredible images of a huge variety of defects. From melted silicon to cracked metallization and all points between, an electron microscope is an invaluable tool for inspecting any anomaly. Electron microscopy services are, of course, only one part of successful failure analysis; though an electron microscope picture might be the culminating piece of data for a failure analysis report, it takes experience and skill to ensure that the electron microscope picture is, in fact, of the defect at the root cause of failure.

An Approach to Capacitor Failure Analysis

The humble capacitor is one of the most fundamental components of any electronic assembly. These ubiquitous passive devices come in a variety of different flavors; whether formed using electrolytic fluids, metal foils, the metals and oxides of an integrated circuit, or any of a multitude of other materials, there is hardly a printed circuit assembly in the world without at least one capacitor mounted somewhere on its surface. Capacitors form the backbone of charge pumps, frequency filters, power conditioners, and many other common applications; since these components are so crucial to these operations, a malfunctioning capacitor can often cause complete failure of a system. At first blush, a capacitor would seem to be a fairly straightforward device to perform analysis on (after all, how complex can two electrodes separated by a thin dielectric be?), capacitor failure analysis poses unique challenges that must be met with equally unique approaches.

As with any project, the ultimate goal in capacitor failure analysis is determining a root cause for failure – in other words, finding whether the improper operation is due to manufacturing imperfections, end-user abuse, or other factors. Just as with an integrated circuit, the first step in the process is determining where an analyst should even begin looking for a failure; after all, failing capacitors rarely give outward indication that they have malfunctioned (though an exception can be found with polarized electrolytic capacitors, which have a tendency to explode violently when abused, much to the chagrin of many an inattentive engineering student). The same set of tools that an analyst uses to ferret out defects on an integrated circuit can also be applied to the analysis of a capacitor, with the addition of a little creativity.

The most common failure mechanism for capacitors is a compromised dielectric causing leakage between the capacitor’s two electrodes. Depending on the type of capacitor, this dielectric may take many forms; one of the most common capacitors, the multi-layer ceramic capacitor often referred to as a chip cap, uses a ceramic material comprised of small particles of various materials blended to achieve a desired set of characteristics. In this type of capacitor, the most common failure is cracking or delamination of the capacitor’s internal layers. An acoustic microscope can be used to detect these damaged dielectrics, just as it might find delamination in an encapsulated integrated circuit; analyzing a capacitor acoustically, however, does not necessarily follow the same course as analyzing a packaged IC.

In a packaged IC, there are two primary acoustic techniques for determining the condition of a package; a plan-view image of the device (referred to as a C-Mode image), and comparisons of the reflected acoustic wave at several points (known as A-Scans). The C-Mode image contains data about a small handful of interfaces within the package (e.g. the die-to-encapsulant interface, or the encapsulant-to-leadframe interface), while variations in phase and amplitude on the A-Scan can be used to identify differences between points that might indicate a defect. A chip cap has many more interfaces than an integrated circuit, with multiple layers of metal and ceramic stacked upon one another; the C-Scan can really only be used to look at one of these interfaces at a time, and as such is not an ideal approach to analyzing the entire device. For a ceramic capacitor, the appropriate technique is a tomographic approach known as a B-Scan – a technique which provides cross-sectional images of the entire thickness of the device.

Using a B-Scan, it is not only to determine the presence of a damaged dielectric in the capacitor, but also its relative location in the device, facilitating a targeted cross-section. Since many capacitor failures result in increased leakage current, many integrated circuit techniques for isolating leakage translate directly to capacitor analysis. While techniques steeped in semiconductor physics like photoemission are of limited utility for capacitor failure analysis, methods of isolating current flow by its secondary effects, like thermal imaging, are more than capable of identifying dielectric pinholes or other leakage sites.

Since these techniques often rely on line-of-sight, they are more useful as a secondary confirmation of a failure, correlating an electrical signature to a physical defect revealed during deconstruction or cross-section of a device. The failures here are only a small incursion into the realm of capacitor failure analysis. Indeed, even devices as seemingly humdrum as the simple capacitor can make for exciting failures; leaking electrolytic capacitors may cause catastrophic failure in the form of burnt circuit boards, tantalum capacitors may explode in a shower of sparks, and high voltage capacitors may break down with a thunderous crack. Despite their simplicity, failure analysis on capacitors is a complex, yet worthwhile endeavor, even if the end result is only an improvement in product reliability instead of the aversion of an uncontrollable conflagration.

Electronics Component Failure Analysis – Isolating Failing Components

The modern electronics consumer is a demanding, discerning individual. The demands placed on any product are extensive; end users expect a wide range of functionality, with high reliability, at low cost. A device as ubiquitous as a smartphone is capable of facilitating transcontinental data transfer, displaying cutting edge graphics, and performing feats of mathematical might, all in a package small enough to fit into a pocket – and at a price point low enough not to empty said pocket. Modern electronic systems require hundreds, if not thousands, of components, all working together in concert to provide the functionality consumers have come to rely on; from the sheer computing power of a cutting-edge microprocessor to the simplicity of a passive capacitor, each component is vital to a device’s operation, since extraneous or redundant parts are trimmed during design in order to minimize costs. When one of these components fail – even one as minor as a surface mount resistor – a device can go from a modern marvel of technology to an extremely expensive inert hunk of plastic and metal. Determining why a device failed is often an excellent first step towards improving the reliability of future generations of products;  electronic component failure analysis is, therefore, a key component in the race for continuous improvement of electronic devices.

While the complexity of modern electronics allows the versatility and functionality end users expect, it can make it difficult to determine where to start in attempting to isolate a failure. A circuit board may be hundreds of square inches of densely packed discrete components, integrated circuits, and wiring; a schematic view may be so intricate as to require several feet of paper to print out. In these cases, electronic component failure analysis gains a whole new aspect of complexity; an analyst must be able to isolate the failing component amongst a plethora of other devices. Analyzing each component inside a device is not a particularly effective approach, nor is it an efficient use of time; exhaustive testing could require hours of an analyst’s time and produce very little actionable data. In order to perform a successful analysis, one must first narrow the field of possibilities to create a more manageable test plan.

By examining a device’s history and reported failure mode, an analyst can create a much more limited list of potential failure mechanisms; through experience, the analyst may choose one or two theories that are the most plausible, in doing so limiting the number of potentially failing components. This process often involves poring over the layouts and schematics for a given product; by getting an in-depth look at the way a device is constructed and how the circuit is intended to work, an analyst can more easily identify likely points of failure. Once an analyst has developed a working theory, the failure analysis project proceeds like any other scientific endeavor; by gathering supporting data.

In order to prove their theory, an analyst must be able to provide concrete data pinpointing the failing component. Sometimes, an analyst might be able to use tools like thermal imaging to generate this data (for example, by identifying a component that is overheating as a result of a short-circuit); in other instances, it is necessary to electrically isolate a potentially failing component from the rest of the circuit. Isolating a failure might be as simple as removing components from the board and checking to see if the reported failure is still present; in more complex cases, it may be necessary to carefully cut traces on a board in order to isolate a device from other parts of the circuit. Immediately following every circuit modification, additional electrical testing is necessary to determine whether the correct component has been identified; once the failing device has been found, failure analysis of the individual electronic component can begin.

While the most glamorous part of any electronics component failure analysis project is the moment where an analyst produces the perfect image or bit of test data that inarguably identifies the root cause of a device’s failure, there is a substantial amount of work that goes into a project before that culminating instant of victory. Though an analyst tracing through schematics, removing components from the board, hunching over a test bench and taking readings off multimeters and curve tracers to determine which component among hundreds may never get the glitzy Hollywood treatment on prime-time television (despite countless attempts to sell a script for the pilot episode of Chip Scale Investigators), these uninspiring tasks are nevertheless a fundamental part of the failure analysis process.

Technical Competitive Analysis Using Failure Analysis Tools

The modern electronics and semiconductor markets are fiercely competitive. Manufacturers are constantly vying for supremacy, attempting to carve out a niche with novel, innovative approaches to fulfill the needs and wants of an increasingly demanding customer base. In such a rapidly changing, fast-paced environment, bringing a new product to market can be challenging, especially without any sort of knowledge of how the competition might measure up. Often, a manufacturer looking to break into the market will employ a third party to perform a technical competitive analysis – an in-depth look at the construction of a product that can provide insight into key details like process node, die size, and functional block size that can be used to perform cost and performance analyses. At first blush, technical competitive analyses appear completely separate from failure analysis services; in reality, the tools and techniques developed for finding defects on cutting-edge products translate seamlessly to the type of teardowns necessary to perform a deep dive into the minutiae of a product’s construction.

In performing failure analysis, the ability to produce the perfect image of a defect is paramount; a crisp, clear photograph of a gate oxide pinhole or metal over-etch can provide a wealth of information to an engineer grappling with catastrophically low yields. Similarly, the right picture is worth a thousand trite clichés when performing a technical competitive analysis. With the same high resolution tools that a failure analyst uses to capture images of melted silicon and metal in the aftermath of an electrical overstress event, it is possible to identify functional blocks on a die, measure the size of a memory cell, and determine the processes used to manufacture a product. High magnification optical images of a product can provide easy-to-interpret, high-level information about a device, while ultra-high resolution electron microscopy can be used to perform circuit extraction, reverse engineering, and process analysis. Of course, just as with failure analysis, there is often a rocky path that must be traversed in order to get to the perfect picture; the sample preparation of a device is just as crucial as the imaging process.

One of the mainstays of the failure analysis process is deprocessing, the act of removing the layers of metal and oxide comprising a device in order to reveal the defects hidden therein. These same techniques are also applicable to technical competitive analysis: in many cases, features of interest are hidden from view (either intentionally or as a consequence of the dense layers of interconnect required in cutting-edge semiconductor products), and must be revealed before any meaningful insight can be gleaned. In many cases, simply removing the metal interconnects to expose the underlying transistors at the polysilicon layer of a device is sufficient; information about functional blocks and process node are easily accessed without the interceding metals obscuring important features. For more in-depth reverse engineering and circuit extraction work, a more methodical, layer-by-layer approach is necessary, so that an expert might be able to trace a signal of interest as it weaves its way through the metallic highways and byways of a circuit. This analytical path is highly targeted towards developing understanding of a device’s circuitry; in order to better understand its construction, other techniques are more suited.

In the same way that cross-sectional analysis is used to view the many layers of an integrated circuit and look for defects or process weaknesses between vertically stacked traces, a cross-section for technical competitive analysis can reveal aspects of a device’s construction that are not readily apparent through deprocessing. The materials used in constructing a device are often equally important as the device’s circuit layout: dielectric composition, the spacing between traces, and the type of metallization used can all greatly impact a device’s performance. Cross-section is also one of the best ways to determine transistor construction characteristics – not just gate length for assessing process node, but atypical transistor constructions that might not be readily apparent from a top-down inspection (for example, the appearance of LDMOS in an RF block of a baseband processor). With the proper sample preparation, an expert can even make inferences about dopant types and profiles based on a cross-sectional inspection.

A very close cousin of technical competitive analysis is intellectual property investigation – specifically, patent infringement analysis. As mentioned, the modern electronics and semiconductor markets are fiercely competitive; so competitive, in fact, that safeguarding one’s intellectual property in order to maintain a technological edge is crucial. Using the same set of aforementioned techniques, a team of analysts can generate a compelling dataset to prove infringement on a client’s IP; in doing so, the client can maneuver themselves into a position of strength for licensing negotiations or IP litigation.

Solder Quality Inspections and Failure Analysis

While solder, the metallic alloy that is melted and reflowed to create joints between components and printed circuit boards, may not be as exciting and glamorous as the intricate webwork of copper and polysilicon in an integrated circuit, it is still vital to the creation of an electronic device. Without proper solder connections, even the most advanced of integrated circuits is reduced to an ineffectual paperweight, lacking any pathways for power and signals to travel over. Being able to perform a solder quality inspection is, therefore, an integral part of any failure analyst’s repertoire of skills.

As with any failure analysis study, solder quality inspections begin with non-destructive tests, in order to try and pinpoint defects without inadvertently eliminating any evidence. X-ray inspection is one of the principal methods of inspecting solder quality non-destructively, as it is easy to characterize joints and generate statistics that can be useful in determining whether to accept or reject a given process. Percent voiding (the area of a given joint where there is a void, or air pocket, in the solder as a percentage of the total area of the joint), ball size, and ball shape (whether the solder balls of a BGA appear round and uniform, or squashed and stretched out of shape) can all provide insight into the reliability of a given solder process. X-ray tomography systems, which produce three-dimensional models of the devices they analyze, can provide an even greater depth of detail of solder joint issues; depending on resolution, they can reveal joint defects, like “head-in-pillow” or non-wetting. Even the relatively minuscule C4 bumps used to connect “flip-chip” die to their substrate can be examined this way; these particular devices are also good candidates for acoustic microscopy at ultra-high frequencies (generally greater than 150MHz), which can reveal cracked or otherwise malformed joints.

While non-destructive test methods provide strong indicators of possible failures or quality issues, they generally need to be corroborated by a more direct view of the failure; destructive testing in solder quality inspections is used to confirm defects noted during non-destructive analysis, and to reveal defects of a size or nature that masked them from less intrusive methods. One of the most common techniques used to analyze solder joints in this fashion is the micro-section; by grinding into and polishing a solder joint, many defects can be viewed and photographed directly. Micro-sectioning also provides information about intermetallic compound (IMC) formation and solder grain structure, both of which can be indicators that can be used to characterize a soldering process. Micro-sectioning provides a high level of detail about a limited number of solder joints on a component; the complementary technique, dye penetrant testing, offers a broader view of all of a component’s joints. By immersing a sample in fluorescent or an otherwise brightly colored dye, then prying the sample from the board, an analyst can locate cracked or non-wetted joints across the whole of a sample.

While imaging techniques and other direct methods of seeing defects are often easiest to understand, generating data through electrical characterization is also an important part of solder quality inspection. Reliability tests, such as HALT or other stress testing, provide important simulated data on how a device might age in the field; following these tests up with the aforementioned techniques provides a more comprehensive dataset for understanding a soldering process. Even very basic tests, like placing a device under bias in an environmental chamber and varying the temperature across the sample’s specified operating range, can reveal defects and process weaknesses that might otherwise go unnoticed.

In some cases, solder quality inspection does not have anything to do with the structure of the solder, but of the materials that comprise it. RoHS certification requires that solder be free of lead, in order to mitigate some of the environmental damage posed by e-waste. Tools like energy dispersive spectroscopy or x-ray fluorescence provide data about the elemental composition of a given sample and can be used to screen a process to ensure that lead-free solder has been used for all components.

Though solder quality inspection may take on a variety of different forms, there is always one point of commonality; all are designed to generate data to act as a springboard for continuous improvement. By more thoroughly understanding the solder processes used to create an electronic device, manufacturers can see potential weaknesses and reliability issues. In-depth analysis of solder quality is, therefore, invaluable for any manufacturer looking to deliver a more robust product.